Hitherto, scan-path self-testing circuits of integrated circuits include a plurality of gates which are selectively enabled under the control of a scan path controller to supply a clock pulse to logic units of a selected scan-path group. The clock gates are provided in a one-to-one correspondence with the scan-path groups. Because of this relationship, the circuit configuration of the gates cannot be determined until the organization of the logic units is determined and must be altered whenever the logic units are reorganized.